1. Field of Invention
The present invention relates to the structure and the manufacturing process of a surrounding-gate flash memory cell. More particularly, the present invention relates to a surrounding-gate flash memory having a self-aligned control gate.
2. Description of the Related Art
The nonvolatile memory cells have been widely used in various electronic components for the storage of structural information, the programming of information or information that can be repeatedly accessable. A flash memory is an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM). Since the information in a flash memory can be stored, read and erased many times, there is increasing demand for the flash memory in the semiconductor market.
Two gates are generally provided in a flash memory cell, one of which is the floating gate formed by polysilicon for the storage of electrical charges. and the other of which is the control gate to control the access of information. The floating gate is located under the control gate and is often in the state of xe2x80x9cfloatingxe2x80x9d without connecting to any circuitry. The control gate is usually connected to a wordline. A characteristic of the flash memory cell is its high speed xe2x80x9cblock-by-blockxe2x80x9d in the erasure of the stored data and is usually accomplished within 1 to 2 seconds. The xe2x80x9cblock-by-blockxe2x80x9d erasure process is much faster than the typical xe2x80x9cbit-by-bitxe2x80x9d EPROM erasure process, which requires at least several minutes.
As the device integration becomes higher, the coupling ratio of a control gate becomes smaller and the operation voltage needs to be raised. The application of the floating gate transistor structure in a conventional flash memory therefore limited in highly integrated circuits. In the trend of increasing the writing and erasure speed and lowering the operation voltage of a flash memory, increasing the coupling ratio of the control gate has become the only solution. The potential of a floating gate can be increased as the coupling ratio of the control gate is increased Increasing the coupling ratio of the control gate, however, is inevitable to increase the capacitance between the floating gate and control gate. One way of increasing the capacitance is to reduce the thickness of the insulation layer, the other way is to increase the area of the capacitor or to use a high dielectric constant insulation material
Based on foregoing, a surrounding-gate flash memory cell having a greater capacitor area between the control gate and the floating gate, and a higher coupling ratio for the control gate at the same integration as a conventional flash memory is provided.
The writing, reading and erasing of a flash memory are related to the coupling ratio of the control gate. The coupling ratio of the control gate of each flash memory cell unit has to be the same to avoid a faulty operation. It is, therefore, very important to control the area of the capacitor between the control gate and the floating gate in each flash memory cell unit. A micro-patterning process is used in forming the control gate of a flash memory in the conventional method. As the device integration gets higher, the window of the photo resist process becomes smaller. In such a case, it is possible to cause a difference in the operational voltage between different flash memory cell units due to misalignment. The flash memory is formed by an array of a plurality of flash memory cell units. A faulty operation thereby occurs when there is a difference in the operational voltage between the cell units in the same flash memory. The present invention is to provide a self-aligned method of forming the control gate and to ensure the same capacitor area between the control gate and the floating gate in each flash memory cell unit.
The same tunneling oxide layer is used for the electron transfer in the programming and the erasure of the information of a conventional floating gate flash memory, which may lead to the damage of the device easily. The present invention further provides a surrounding-gate flash memory comprising of control gates, floating gates and erasure gates. Moreover, the writing and the erasure of information are carried out at different silicon oxide layers to prevent the device from being damaged and to increase the lifetime of the device.
According to the present invention, a surrounding-gate flash memory having self-aligned control gates is provided. Such surrounding-gate flash memory is disclosed as the following:
A plurality of device isolation structures formed by a shallow trench isolation method or by a local oxidation method, are provided on a substrate. These device isolation structures are arranged in the form of a chessboard, with one row as a region and each region containing a plurality of the device isolation structures. The source regions are located in the substrate and are between neighboring regions of the device isolation structures. The tunneling silicon oxide layers are located at both ends of each device isolation structure region and on the substrate the source regions are located. The drain regions are located in the substrate without the tunneling oxide layer which are located between each two device isolation structures in the same region and two drain regions are isolated by the device isolation structures in the same region.
A group of polysilicon block comprises a polysilicon block extended across the same ends of every two device isolation structures, above the tunnel oxide layer. On the other ends of the same device isolation structures also extends another polysilicon block to form the other group of polysilicon block. Thus, two groups of polysilicon block are present in a same region of the device isolation structures. These polysilicon blocks are used as floating gates and these polysilicon blocks are located above the tunneling oxide layer. The distance between a polysilicon block and an adjacent polysilicon block is not the same. The distance between the polysilicon blocks in the same group is smaller than that in different groups. The distance between the polysilicon blocks in the same group is also smaller than the distance between the device isolation structures in the same region. A silicon oxide cap formed by local oxidation is provided over each polysilicon block. A first silicon oxide layer is formed on the sidewall of each polysilicon block. These silicon oxide layers are positioned above the tunneling oxide layers as well.
Referring to FIGS. 3a and 3b, using the patterned photoresist layer 126 as a mask, the mask layer 124 is etched to form the mask layer 124 having openings 130 and 130a. The mask layer 124 is etched by, for example, anisotropic etching. The openings 130 and 130a expose the polysilicon layer 121 thereunder. Thereafter, the photoresist 126 is removed. Field silicon oxide isolation layer 102 is formed on the polysilicon layer 121 by local oxidation using the mask layer 124a as a mask.
First polysilicon layers are provided on the sidewalls of the polysilicon blocks and above the tunneling oxide layers to connect the polysilicon blocks in the same group and separated from the polysilicon blocks by the first silicon oxide layer. The height of the first polysilicon layer is lower than that of the polysilicon blocks. These first polysilicon layers are used as control gates and as word lines. Second silicon oxide layers are provided on the surfaces of the first polysilicon layers. Further, the second polysilicon layers are provided above the tunnel silicon oxides above the sources. These second polysilicon layers located on the device isolation structures in the different regions but in between the adjacent polysilicon blocksform a T-shaped structure, which covers the half parts of the polysilicon blocks adjacent to the sources. These second polysilicon layers are used as erasure gates.
A dielectric layer covers all of the above constituting elements. Plugs are provided in the dielectric layer. The lower end of one plug is electrically connected to the drain. Conductive lines are provided above the dielectric layer and the conductive lines do not intersect. Each conductive line is electrically connected to the upper end of one plug exposed in the surface of the dielectric layer, and only connected to one of the drains in each group of the drains by one plug. These conductive lines are used as bit lines.
Further, two dummy polysilicon blocks which are side-by-side and having a smaller size are provided at both ends of each group of the polysilicon blocks. The dummy polysilicon blocks is to provide the position for forming the conductive plugs of the control gates.
According to the preferred embodiment of the present invention, a method for fabricating the above structure of the surrounding-gate flash memory having self-aligned control gates is provided. A substrate is first provided. Device isolation structures are provided on the substrate. The device isolation structures are roughly parallel to each other, and arranged in the form of a chessboard. Each row of the device isolation structures form a region and every region of the device isolation structures includes a plurality of the device isolation structures. A strip-shaped source region is provided between each two regions of the device isolation structures. A block-shaped drain region is provided between the device isolation structures in each region. The method of forming these device isolation structures comprises shallow trench isolation or local oxidation.
On the surface of the substrate, a tunnel silicon oxide and a first polysilicon layer are sequentially formed. The method of forming the tunneling oxide layer comprises thermal oxidation. The method of forming the first polysilicon layer comprises chemical vapor deposition. A field silicon oxide isolating layer is formed by local oxidation over the first polysilicon layer. The polysilicon layer is etched by using the field silicon oxide isolation as mask. A polysilicon block and a dummy polysilicon block having the field silicon oxide isolating layer. The method of etching the first polysilicon layer includes selectively anisotropic etching.
A patterned photoresist layer is formed by the known lithography to allow said strip-shaped source region to be exposed. The source is formed in the source region. The method of forming the source includes ion implantation. The photoresist layer is removed. A first silicon oxide is formed on the sidewall around the polysilicon block. The method of forming the first silicon oxide includes thermal oxidation.
A conformal second polysilicon is formed over said substrate. The method of forming the polysilicon layer includes low-pressure chemical vapor deposition or plasma-enhanced vapor deposition. The conformal polysilicon layer is etched. The second polysilicon layer is etched and the tunneling oxide layer is used as etching-stop layer. The method of etching polysilicon layer includes selectively anisotropic etching of the polysilicon/silicon oxide.
A second silicon oxide is formed on the surface of said the etched second polysilicon layer. The method of forming the second silicon oxide includes thermal oxidation or chemical vapor deposition. A third polysilicon layer is formed over the whole surface of the substrate. The method of forming the third polysilicon layer includes chemical vapor deposition. A plurality of openings is formed in said third polysilicon layer. The drain regions, a part of the second silicon oxide and a part of said field silicon oxide isolating layer are exposed through the openings. The method of forming the openings includes known lithography and anisotropic etching. Drains are formed in the drain region. The method of forming the drains includes ion implantation. The tunneling silicon oxide located over the drains is removed.
A dielectric layer is formed. The method of forming the dielectric layer includes chemical vapor deposition. The dielectric layer covers all of the constituting elements. The material for the dielectric layer includes silicon oxide. Plugs are formed by known process for forming plugs in the dielectric layer. The lower ends of the plugs are electrically connected to the drains, and the upper ends thereof are exposed on the surfaces of the dielectric layer. A plurality of conductive lines is formed over the dielectric layer by known process to be connected to the upper ends of the plugs.